Senior UVM Verification Architect for Interface IP in Dublin

Synopsys, Inc. requires a senior verification engineer to architect UVM-based testbenches for interface IP in silicon designs. The role involves writing constrained-random sequences and implementing SV assertions to ensure robust verification processes. The candidate will mentor a team, drive coverage metrics, and contribute to functional and formal verification flows. This position aims to accelerate tape-out schedules through effective verification strategies and leadership.

Location and applying

The full responsibilities and requirements are not available here. Use the apply button to view the vacancy at www.jobg8.com.